Independent Gate Finfet Sram Cell Using Leakage Reduction Techniques

1 Research Scholar of Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India 2 Professor, Dept. of Electronics and Communication, Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India. __________________________________________________________________________________________ Abstract: Scaling of devices in bulk CMOS technology contributes to short channel effects and increase in leakage. Static random access memory (SRAM) is needed to occupy 90% of the area of SoC. Since leakage becomes the important factor in SRAM cell, it is implemented using FinFET. FinFET devices became better alternative for deep submicron technologies. In this paper, 6T SRAM cell is implemented using independent gate FinFET in which both the opposite side of gates are operated independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as Multi threshold voltage, and Gated-VDD technique to reduce leakage current, power consumption in the SRAM cell and provides better performance. The Proposed FinFET based 6T SRAM cell has been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm Technology.